The NXP i.MX8QXP CPU has eight GPIO ports. Each port can generate and control 32 signals.

The MCA also features a number of GPIO pins (multiplexed with Analog-to-Digital Converter (ADC) functionality). See MCA General Purpose Input/Output (GPIO) for additional information on MCA GPIOs.

GPIOs on the ConnectCore 8X platforms

  • On the ConnectCore 8X system-on-module:

    • Many of the i.MX8QXP GPIOs are available at the system-on-module, multiplexed with other functions (labeled GPIOx_IOy where x is the port and y is the GPIO pin). See Hardware reference manuals for information about GPIO pins and their multiplexed functionality.

    • 19 MCA GPIO pins are available (labeled MCA_IOx where x is the GPIO pin).

  • On the ConnectCore 8X SBC Express, the expansion connector allows direct access to several i.MX8QXP GPIOs and MCA GPIOs.

  • On the ConnectCore 8X SBC Pro, the expansion connector allows direct access to several i.MX8QXP GPIOs and MCA GPIOs.

GPIOs on the SOM and carrier board are used for many purposes, such as:

  • Power enable line for transceivers

  • Reset line for controllers

  • LCD backlight control

  • Interrupt line

  • User LED

  • User button

Kernel configuration

You can manage the user space interface with GPIOs through the kernel configuration options:

  • /sys/class/gpio/…​ (sysfs interface) (CONFIG_GPIO_SYSFS)

This option is enabled as built-in on the default ConnectCore 8X kernel configuration file.

Support for i.MX8QXP GPIOs is automatically provided through the non-visible option CONFIG_GPIO_MXC.

Kernel driver

The driver for the i.MX8QXP GPIO is located at:

File Description

drivers/gpio/gpio-mxc.c

i.MX8QXP GPIO driver

Device tree bindings and customization

The i.MX8QXP GPIO device tree binding is documented at Documentation/devicetree/bindings/gpio/fsl-imx-gpio.txt.

One GPIO controller is defined for each i.MX8QXP GPIO port in the common i.MX8QXP device tree file:

i.MX8QXP device tree
	gpio0: gpio@5d080000 {
		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
		reg = <0x0 0x5d080000 0x0 0x10000>;
		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		power-domains = <&pd_lsio_gpio0>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};
 
[...]
 
	gpio7: gpio@5d0f0000 {
		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
		reg = <0x0 0x5d0f0000 0x0 0x10000>;
		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		power-domains = <&pd_lsio_gpio7>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

The ConnectCore 8X device tree include file and the carrier board device tree files use the i.MX8QXP GPIOs.

For example, on the ConnectCore 8X, GPIO3_IO09 is used to activate internal circuitry during the MCA firmware update:

ConnectCore 8X device tree
	mca_cc8x: mca@63 {
		compatible = "digi,mca_cc8x";
		reg = <0x63>;
		interrupt-parent = <&wu>;
		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <2>;
		fw-update-gpio = <&gpio3 9 GPIO_ACTIVE_LOW>;
 
		[...]
};

For example, on the ConnectCore 8X SBC Pro, GPIO3_IO18 is used to reset the PHY of ENET1 Ethernet interface:

ConnectCore 8X SBC Pro device tree
&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec_mdio>,
		    <&pinctrl_fec_gpio>,
		    <&pinctrl_fec1_gpio>,
		    <&pinctrl_fec1>;
	clocks = <&clk IMX8QXP_ENET0_IPG_CLK>,
		 <&clk IMX8QXP_ENET0_AHB_CLK>,
		 <&clk IMX8QXP_ENET0_REF_50MHZ_CLK>,
		 <&clk IMX8QXP_ENET0_PTP_CLK>,
		 <&clk IMX8QXP_ENET0_TX_CLK>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy1>;
	phy-supply = <&reg_3v3_eth0>;
	phy-reset-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <1>;
	fsl,magic-packet;
 
	[...]
};

IOMUX configuration

Pads that are to be used as GPIOs must be configured as such. See Pin multiplexing (IOMUX).

When GPIOs are managed by other drivers, pinctrl-0 configures a set of pads to work according to the specified interface functionalities. In the example below, pinctrl_usdhc2_gpio configures GPIO5_IO09 as a card detect line for the microSD card:

ConnectCore 8X device tree
	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
		fsl,pins = <
			/* Card detect */
			SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09	0x06000021
		>;
	};

For GPIOs that are not associated with any interface or that can’t be handled by a driver, you can define the IOMUX in the pinctrl_hog node of the device tree IOMUX section. For example, GPIO0_IO19 is routed to the user LED and GPIO0_IO20 to the user button of the ConnectCore 8X SBC Express:

ConnectCore 8X SBC Express device tree
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_hog: hoggrp {
		fsl,pins = <
			/* User LED */
			SC_P_MCLK_IN0_LSIO_GPIO0_IO19	0x06000020
			/* User button */
			SC_P_MCLK_OUT0_LSIO_GPIO0_IO20	0x06000020
		>;
	};

Using the GPIOs

You can access the GPIOs from your Android application. See GPIO API for more information about the GPIO APIx.

Calculate the Linux GPIO number of a GPIO pin

For each GPIO controller entry on the device tree, Linux creates an entry /sys/class/gpio/gpiochipN, where N is calculated as per the formula:

N = (512 - <n_gpios>) - (<n_gpios> * <port_index>)

Each entry has the following read-only attributes:

  • base: same as N, the first GPIO managed by this chip

  • label: provided for diagnostics (not always unique)

  • ngpio: the number of GPIOs this controller manages (from N to N + ngpio - 1)

GPIOs on the ConnectCore 8X system-on-module

Every GPIO port of the i.MX8QXP CPU is a different GPIO controller and thus has its own /sys/class/gpio/gpiochipN entry on the sysfs.

On the default ConnectCore 8X system-on-module device tree, the i.MX8QXP CPU’s GPIO ports are probed first. Considering each one has 32 GPIOs, the formula results:

N = 480 - (32 * <port_index>)
  • GPIO0: /sys/class/gpio/gpiochip480

  • GPIO1: /sys/class/gpio/gpiochip448

  • GPIO2: /sys/class/gpio/gpiochip416

  • GPIO3: /sys/class/gpio/gpiochip384

  • GPIO4: /sys/class/gpio/gpiochip352

  • GPIO5: /sys/class/gpio/gpiochip320

  • GPIO6: /sys/class/gpio/gpiochip288

  • GPIO7: /sys/class/gpio/gpiochip256

Calculate the Linux GPIO number for a certain GPIO pin by adding the GPIO pin index to the port base index. For instance:

i.MX8QXP GPIO2_IO4 (port 2, pin 4) is: 416 + 4 = 420.

The following formula applies to i.MX8QXP CPU GPIOs (without requiring the user to know the GPIO base of each port):

\$"LinuxGPIO_num" = 480 - (32 * "<port_index>") + "<gpio_pin>"\$

For instance, i.MX8QXP GPIO2_IO4 (port 2, pin 4) is:

\$480 - (32 * color(red)(2)) + color(red)(4) = 420\$

Sample application

The GPIO Sample Application demonstrates the usage of the GPIO API. In this example, one GPIO is configured as input and another as output. You can press the virtual button to switch on and off the User 0 LED corresponding to the output GPIO.

Go to GitHub to see the application instructions and source code.

See MCA General Purpose Input/Output (GPIO) for additional information on MCA GPIOs.