The NXP i.MX8QXP CPU has two 10/100/1000 Ethernet MACs.

On the ConnectCore 8X SBC Pro:

  • Ethernet1 port is connected to a 10/100/1000 Atheros AR8031 PHY.

  • Ethernet2 port is connected to a 10/100/1000 Atheros AR8031 PHY.

Kernel configuration

You can manage the Ethernet driver and PHY Device support through the following kernel configuration options:

  • FEC Ethernet controller (of ColdFire and some i.MX CPUs) (CONFIG_FEC)

  • PHY device support for LAN83C185, LAN8187 and LAN8700 (CONFIG_SMSC_PHY)

  • PHY device support for AT803x (CONFIG_AT803X_PHY)

These options are enabled as built-in on the default ConnectCore 8X kernel configuration file.

Kernel driver

The driver for the Ethernet interface is located at:

File Description

drivers/net/ethernet/freescale/fec_main.c

i.MX FEC driver

drivers/net/phy/smsc.c

Driver for Microchip LAN8720a PHY

drivers/net/phy/at803x.c

Driver for Atheros 8031 PHY

Device tree bindings and customization

The i.MX8QXP Ethernet interface device tree binding is documented at Documentation/devicetree/bindings/net/fsl-fec.txt. The Ethernet interfaces are defined in the i.MX8QXP CPU, ConnectCore 8X SBC Express, and ConnectCore 8X SBC Pro device tree files.

Example: FEC1 & FEC2 on ConnectCore 8X SBC Pro

Definition of the FECs

i.MX8QXP device tree
fec1: ethernet@5b040000 {
	compatible = "fsl,imx8qm-fec";
	reg = <0x0 0x5b040000 0x0 0x10000>;
	interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, <&clk IMX8QXP_ENET0_AHB_CLK>, <&clk IMX8QXP_ENET0_RGMII_TX_CLK>,
		<&clk IMX8QXP_ENET0_PTP_CLK>, <&clk IMX8QXP_ENET0_TX_CLK>;
	clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
	assigned-clocks = <&clk IMX8QXP_ENET0_ROOT_DIV>,
			  <&clk IMX8QXP_ENET0_REF_DIV>;
	assigned-clock-rates = <250000000>, <125000000>;
	fsl,num-tx-queues=<3>;
	fsl,num-rx-queues=<3>;
	power-domains = <&pd_conn_enet0>;
	status = "disabled";
};

fec2: ethernet@5b050000 {
	compatible = "fsl,imx8qm-fec";
	reg = <0x0 0x5b050000 0x0 0x10000>;
	interrupt-parent = <&wu>;
	interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8QXP_ENET1_IPG_CLK>, <&clk IMX8QXP_ENET1_AHB_CLK>, <&clk IMX8QXP_ENET1_RGMII_TX_CLK>,
		<&clk IMX8QXP_ENET1_PTP_CLK>, <&clk IMX8QXP_ENET1_TX_CLK>;
	clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
	assigned-clocks = <&clk IMX8QXP_ENET1_ROOT_DIV>,
			  <&clk IMX8QXP_ENET1_REF_DIV>;
	assigned-clock-rates = <250000000>, <125000000>;
	fsl,num-tx-queues=<3>;
	fsl,num-rx-queues=<3>;
	fsl,wakeup_irq = <0>;
	power-domains = <&pd_conn_enet1>;
	status = "disabled";
};

IOMUX configuration

ConnectCore 8X SBC Pro device tree
/* FEC shared MDIO bus */
pinctrl_fec_mdio: fecmdiogrp {
	fsl,pins = <
		SC_P_ENET0_MDC_CONN_ENET0_MDC		0x06000020
		SC_P_ENET0_MDIO_CONN_ENET0_MDIO		0x06000020
	>;
};

/* Shared GPIOs */
pinctrl_fec_gpio: fecgpiogrp {
	fsl,pins = <
		/* PHY power */
		SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13		0x06000021
	>;
};

pinctrl_fec1_gpio: fec1gpiogrp {
	fsl,pins = <
		/* PHY reset */
		SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18	0x06000021
		/* PHY interrupt */
		SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28	0x06000021
	>;
};

pinctrl_fec1: fec1grp {
	fsl,pins = <
		SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x00000060
		SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x00000060
		SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x00000060
		SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x00000060
		SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x00000060
		SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x00000060
		SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x00000060
		SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000060
		SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x00000060
		SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x00000060
		SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x00000060
		SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x00000060
	>;
};

pinctrl_fec2_gpio: fec2gpiogrp {
	fsl,pins = <
		/* PHY reset */
		SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22		0x06000021
		/* PHY interrupt */
		SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00	0x06000021
	>;
};

pinctrl_fec2: fec2grp {
	fsl,pins = <
		SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL		0x00000060
		SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC		0x00000060
		SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0	0x00000060
		SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1	0x00000060
		SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2		0x00000060
		SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3		0x00000060
		SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC		0x00000060
		SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL		0x00000060
		SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0		0x00000060
		SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1	0x00000060
		SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2	0x00000060
		SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3		0x00000060
	>;
};

Ethernet enabling and PHY parameters

ConnectCore 8X SBC Pro device tree
&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec_mdio>,
		    <&pinctrl_fec_gpio>,
		    <&pinctrl_fec1_gpio>,
		    <&pinctrl_fec1>;
	clocks = <&clk IMX8QXP_ENET0_IPG_CLK>,
		 <&clk IMX8QXP_ENET0_AHB_CLK>,
		 <&clk IMX8QXP_ENET0_REF_50MHZ_CLK>,
		 <&clk IMX8QXP_ENET0_PTP_CLK>,
		 <&clk IMX8QXP_ENET0_TX_CLK>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy1>;
	phy-supply = <&reg_3v3_eth0>;
	phy-reset-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <1>;
	fsl,magic-packet;
	digi,phy-reset-in-suspend;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
			at803x,eee-disabled;
			at803x,vddio-1p8v;
		};

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
			at803x,eee-disabled;
			at803x,vddio-1p8v;
		};
	};
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec2_gpio>,
		    <&pinctrl_fec2>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	phy-supply = <&reg_3v3_eth0>;
	phy-reset-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <1>;
	fsl,magic-packet;
	status = "okay";
};

MAC addresses

The MAC addresses of the i.MX8QXP Ethernet interfaces are programmed in the U-Boot environment (variables ethaddr and eth1addr) on the ConnectCore 8X eMMC. The MAC address of the first Ethernet interface is also printed on the module label. U-Boot writes the MAC addresses in the ethaddr and ethaddr1 environment variables into their respective device tree fec nodes under the local-mac-address property.

Using the Ethernet interface

For information about using Ethernet interfaces, see Networking API.