Quick Version: How (if possible) can I tell if an assembly instruction will access unaligned memory on a Rabbit 6000, and thus correctly determine the number of clocks an ISR will take up.
If you look at the cycle requirements for the various assembly instructions which can be used in Dynamic C, you'll see that unaligned access can nearly double the clocks required for some operations. I'm using 4 serial ports on an RCM6600W, and trying to determine safe speed caps for baud rates. I'd like to push one of the rates up to about 10^6, and assume the others will never go higher than 115200 (while simultaneously using the ethernet and wifi). Depending on whether access is generally aligned or unaligned, I may need to write a custom ISR for the high speed port to shave off some clock cycles, or lower the baud rate for that port.