Buffered Data/Address Lines

Question

I am interfacing to an FPGA using buffered address/data lines. When I mmap using CS2 at address 0x60000000 I find that data lines D0 thru D7 are actually "multiplexed" onto data lines D8 thru D15. Buffered data lines D0 thru D7 appear to do nothing? Anyone else come across this quirk? Looking on an oscilloscope at the BD8 output, if I write 0x0100 I can see the BD8 data line pulse high for the second half of the write cycle, if I write 0x0101 I can see BD8 pulse high for double the width, starting at the first half of the write cycle, but BD0 stays low? Any thoughts please......

Answer 1

RESOLVED: Okay, now I understand. The ARM processor uses only D8 thru D9 for transferring up to 32 bit words so transfers 4 8 bit bytes per "address". A0 and A1 actually control the byte within a specific address defined by A2 thru A17 thus the "multiplexing" is unravelled. For my FPGA application where 1, 8 bit, byte per address is sufficient it is simplest to just repeat that byte 4 times in a long word. If anyone wishes to see the code for mapping the FPGA addresses into user space just let me know