The NXP i.MX8QXP Cortex A35 has four LPUART interfaces that can be used for serial communication with devices either directly or through level adapters.

On LPUART0, LPUART1, and LPUART3 you can use the RTS and CTS hardware flow-control lines, while LPUART2 is only two-wires (RX/TX).

The NXP i.MX8QXP Cortex M4 has one additional UART interface for general purpose.

LPUART interfaces don’t support 7-bit transfers with no parity; so 7-bit transfers have to be done using odd or even parity.

On the ConnectCore 8X system-on-module:

  • LPUART1 is connected to the Bluetooth chip (on modules with Bluetooth).

  • LPUART0, LPUART2, and LPUART3 are available for peripheral use.

  • M4 UART0 is available for peripheral use.

The MCA in the ConnectCore 8X system-on-module also supports one or more UARTs depending on the firmware version.

See MCA UART serial port for additional information on MCA UARTs.

On the ConnectCore 8X SBC Express:

  • LPUART0 is routed to the XBee socket (four wires: RX/TX/RTS/CTS), multiplexed with CAN0.

    By default, Digi Embedded Yocto assumes the UART routed to the XBee connector is used for connecting an XBee cellular modem. The ModemManager service generates some traffic in this UART in order to detect the XBee during boot and resume operations.

    If you are not using an XBee cellular modem disable this feature by commenting all the entries in the following udev rules file: /lib/udev/rules.d/78-mm-digi-xbee-cellular.rules

    If you are using a different UART to connect to the XBee socket, edit the udev rules file with the appropriate path. Note that the UART node may also change depending on the number of UARTs you enable on the device tree.

    This file is installed by the modemmanager recipe append.

  • LPUART2 is routed to the console connector (two wires: RX/TX).

  • LPUART3 is routed to the Raspberry Pi expansion connector (two wires: RX/TX), multiplexed with M4 UART.

  • M4 UART is routed to the Raspberry Pi expansion connector (two wires: RX/TX), multiplexed with LPUART3.

Castellated pads 70 (SCU_GPIO0_00) and 71 (SCU_GPIO0_01) that carry M4 UART/LPUART3 RX/TX signals, come from the System Controller Unit (SCU) power domain and are thus powered at 1.8V. There is a level shifter on the SBC Express board to adapt these lines to 3.3V before they reach the Raspberry Pi expansion connector. Additionally, 0-ohm resistors have been added in case you want to bypass the level shifter and route the 1.8V lines directly to the connector.

On the ConnectCore 8X SBC Pro:

  • LPUART0 is routed to the expansion connector (four wires: RX/TX/RTS/CTS), multiplexed with CAN0.

  • LPUART2 is routed to the console connector (two wires: RX/TX).

  • LPUART3 is routed to the expansion connector through an RS-485 transceiver with A and B differential lines and is multiplexed with CAN2.

    See RS-485 support for details on RS-485 configuration.

Kernel configuration

You can manage the LPUART support through the kernel configuration options:

  • Freescale lpuart serial port support (CONFIG_SERIAL_FSL_LPUART)

  • Console on Freescale lpuart serial port (CONFIG_SERIAL_FSL_LPUART_CONSOLE)

Kernel driver

File Description

drivers/tty/serial/fsl_lpuart.c

LPUART driver

Device tree bindings and customization

The i.MX8QXP Cortex A35 LPUART interface device tree binding is documented at Documentation/devicetree/bindings/serial/fsl-lpuart.txt

RS-485 support

RS-485 is a standard defining the electrical characteristics of drivers and receivers in balanced digital multipoint systems. RS-485 only specifies electrical characteristics of the generator and the receiver; it does not specify or recommend a communications protocol.

The i.MX8QXP serial driver includes support for the RS-485 standard. No specific kernel configuration is necessary to support RS-485 over the serial interface. The device tree bindings are documented at Documentation/devicetree/bindings/serial/rs485.txt

RS-485 half-duplex needs the RX and TX lines for data communication and the RTS line to control the RS-485 transceiver to either drive output or receive input from outside the chip.

To enable RS-485 mode on an LPUART port, apply the following changes to the device tree node:

  • Add property linux,rs485-enabled-at-boot-time.

  • If using the native RTS line of the UART:

    • Add property rs485-rts-active-low to configure the native RTS line polarity as ACTIVE LOW during transmission.

  • If using a standard GPIO as RTS line:

    • Add property digi,rts-gpio to use a standard GPIO as RTS line. Use macros GPIO_ACTIVE_LOW or GPIO_ACTIVE_HIGH on this property to define the polarity of this GPIO.

Limitations

The following list contains LPUART driver limitations for RS-485:

  • rs485-rts-delay and rs485-rx-during-tx device tree properties are not supported.

  • When using a standard GPIO as RTS line, DMA is disabled.

Example: RS-485 on ConnectCore 8X SBC Pro

By default, only LPUART3 on the ConnectCore 8X SBC Pro device tree is configured in RS-485 mode:

  • LPUART3 is routed to the expansion connector through an RS-485 transceiver with A and B differential lines.

    LPUART3 port is multiplexed with CAN2 port.

    Only one of lpuart3 and flexcan2 nodes should be enabled at a time. lpuart3 is disabled by default.

    CAN/RS485# signal selects between the CAN and RS485 transceivers. To select the RS-485 transceiver, CAN/RS485# signal needs to be driven low. This is handled automatically through the pinctrl-assert-gpios device tree entry.

  • LPUART3 native RTS line is routed to the microSD card so a different GPIO (RS485_RE#/DE = GPIO3_IO24) is routed to the RS485 transceiver instead. Define this GPIO as the RS-485 RTS line with ACTIVE HIGH polarity in the digi,rts-gpio device tree property.

    ConnectCore 8X SBC Pro device tree
    /*
     * LPUART3 on expansion header.
     * Conflicts with CAN2.
     * Requires signal CAN/RS485# (GPIO3_IO23) to be driven low
     */
    &lpuart3 {
    	pinctrl-names = "default";
    	pinctrl-0 = <&pinctrl_lpuart3>,
    		    <&pinctrl_flexcan3_lpuart3_gpios>;
    	pinctrl-assert-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
    	/* Enable RS-485 mode */
    	linux,rs485-enabled-at-boot-time;
    	digi,rts-gpio = <&gpio3 24 GPIO_ACTIVE_HIGH>;
    };

UART user space usage

The i.MX8QXP LPUART bus driver exposes device data through the sysfs at /sys/class/tty/ttyLPN/, where N is the port index, starting at zero.

UART device interface

You can access i.MX8QXP LPUART devices from user space through the device node /dev/ttyLPN, where N is the port index, starting at zero.

The MCA in the ConnectCore 8X system-on-module also supports one or more UARTs depending on the firmware version. See MCA UART serial port for additional information on MCA UARTs.

For information about using the serial port from user space, see the Serial Programming Guide for POSIX Operating Systems.